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? semiconductor components industries, llc, 2015 may, 2015 ? rev. 3 1 publication order number: ncp3231a/d ncp3231a high current synchronous buck converter the ncp3231a is a high current, high efficiency, voltage?mode synchronous buck converter which operates from 4.5 v to 18 v input and generates output voltages down to 0.6 v at up to 25 a. features ? wide input voltage range from 4.5 v to 18 v ? 0.6 v internal reference voltage ? 500 khz switching frequency ? external programmable soft?start ? lossless low?side fet current sensing ? output over?voltage protection and under?voltage protection ? system over?temperature protection using a thermistor or sensor ? hiccup mode operation for all faults ? pre?bias start?up ? adjustable output voltage ? power good output ? internal over?temperature protection ? this is a pb?free device* typical applications ? cellular base stations ? asic, fpga, dsp and cpu core and i/o supplies ? telecom and network equipment ? server and storage system *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. qfn40 6x6, 0.5p case 485cm device package shipping ? ordering information NCP3231AMNTXG qfn40 (pb?free) 2500 / tape & reel marking diagram ncp3231a = specific device code a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package ncp3231a awlyywwg 1 www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. pin connections vin ep42 gnd ep41 vswh ep43 15 14 13 12 11 20 19 18 17 16 36 37 38 39 40 31 32 33 34 35 25 24 23 22 21 30 29 28 27 26 6 7 8 9 10 1 2 3 4 5 vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd en vcc vb pgnd bst vsw vswh vswh vswh vswh pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd vswh vswh vin vin vin pg ots agnd iset comp fb ss (top view) 40 1
ncp3231a www. onsemi.com 2 figure 1. ncp3231a block diagram control logic ramp generator pwm logic ? and ? uvlo ovp, uvp power good ocp, tsd protection soft start osc ldo vref + ? + ? vref e/a pvdd vb vcc vdd vb vcc 1.2 v enable logic por vb vb vb vcc vb comp fb ss en pg agnd bst vin vswh vsw pgnd ots iset 2 a
ncp3231a www. onsemi.com 3 pin description pin no. symbol description 1 ss a capacitor from this pin to gnd allows the user to adjust the soft?start ramp time. 2 fb output voltage feedback. 3 comp output of the error amplifier. 4 iset a resistor from this pin to ground sets the over?current protection (ocp) threshold. 5 agnd analog ground. 6 ots negative input of internal thermal comparator. tie this pin to ground if not in use. 7 pg power good indicator of the output voltage. open?drain output. connect pg to vdd with an external resistor . 8?14, ep42 vin the vin pin is connected to the internal power nmos switch. the vin pin has high di/dt edges and must be decoupled to ground close to the pin of the device. 15, 29?34, ep43 vswh the vswh pin is the connection of the drain and source of the internal nmos switches. at switch off, the inductor will drive this pin below ground as the body diode and the nmos conducts with a high dv/dt. 16?28, 37 pgnd ground reference and high?current return path for the bottom gate driver and low - side nmos . 35 vsw ic connection to the switch node between the top mosfet and bottom mosfet. return path of the high? side gate driver. 36 bst top gate driver input supply, a bootstrap capacitor connection between the switch node and this pin. 38 vb the internal ldo output and input supply for the ncp3231a. connect a minimum of 4.7 f ceramic capacit- or from this pin to ground. 39 vcc input supply for ic. this pin must be connected to vin. 40 en logic control for enabling the switcher. an internal pull?up enables the device automatically. the en pin can also be driven high to turn on the device, or low to turn off the device. a comparator and precision reference allow the user to implement this pin as an adjustable uvlo circuit. ep41 gnd exposed pad. connect gnd to a large copper plane at ground potential to improve thermal dissipation.
ncp3231a www. onsemi.com 4 figure 2. typical application circuit fb en vin bst vswh vsw pgnd comp ots pg vb ss ncp3231a vin vout vpg iset vcc agnd absolute maximum ratings (measured vs. gnd pad, unless otherwise noted) rating symbol value unit power supply to gnd vin, vcc 20.5 ?0.3 v vsw to gnd vswh, vsw 26 ?0.6 (dc) +35 (t < 50 ns) ?5 (t < 100 ns) v bst to gnd bst 30 (dc) ?0.6 (dc) +40 (t < 50 ns) v all other pins 6.0 ?0.3 v operating ambient temperature range (note 1) t a ?40 to +90 c operating junction temperature range (note 1) t j ?40 to +150 c maximum junction temperature t j(max) +150 c storage temperature range t stg ?55 to +150 c electrostatic discharge ? human body model hbm 1.0 kv electrostatic discharge ? charge device model cdm 2.0 kv thermal information hs fet junction-to-case thermal resistance (note 2) r jc?hs 1.3 c/w ls fet junction-to-case thermal resistance (note 2) r jc?ls 0.6 c/w stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja 2. r jc thermal resistance is obtained by simulating a cold plate test on the exposed power pad. no specific jedec standard test exist s, but a close description can be found in the ansi semi standard g30?88.
ncp3231a www. onsemi.com 5 electrical characteristics (?40 c < t j < +125 c, v cc = 12 v, for min/max values unless otherwise noted, t j = +25 c for typical values) parameter symbol test conditions min typ max units power supply vin/vcc operation voltage vin/vcc 4.5 18 v vb uvlo threshold (rising) 4.1 4.2 4.3 v vb uvlo threshold (falling) 3.4 3.66 3.8 v vb output voltage vb vcc = 6 v, 0 ib 40 ma 4.9 5.15 5.45 v vb dropout voltage ib = 25 ma, vcc = 4.5 v 36 110 mv vcc quiescent current en = h, comp = h, no switching; pg open; no switching 4.7 6.4 ma shutdown supply current ncp3231a; en = 0; v cc = 18 v; pg open 100 140 a ncp3231a; en = 0; v cc = 4.5 v; pg open 53 75 a feedback voltage fb input voltage vfb t j = 25 c, 4.5 v vcc 18 v 597 600 603 mv ?40 c t j 125 c; 4.5 v vcc 18 v 594 600 606 feedback input bias current ifb vfb = 0.6 v 75 na error amplifier open loop dc gain guaranteed by design 60 85 db open loop unity gain bandwidth f0db,ea 24 mhz open loop phase margin 60 slew rate comp pin to gnd = 10 pf 2.5 v/ comp clamp voltage, high 3.46 v comp clamp voltage, low 465 mv output source current vfb = 0 v 15 m a output sink current vfb = 1 v 20 m a current limit low?side iset current source ls_iset sourced from iset pin, before ss, t j = 25 c 34 a low?side iset current source temperature coefficient tc_ls_i? set +0.31 %/ c low?side ocp switch?over threshold guaranteed by design 600 mv low?side fixed ocp threshold ls_ocpth guaranteed by design 300 mv low?side programmable ocp range ls_ocpth < 600 mv ls ocp blanking time ls_tblnk guaranteed by design 150 ns pwm maximum duty cycle fsw = 500 khz, vfb = 0 v 4.5 v < vcc < 18 v 92 % minimum duty cycle vcomp < pwm ramp offset voltage 0 % minimum gh on?time guaranteed by characterization 60 ns pwm ramp amplitude guaranteed by characterization vcc/8.6 vcc/6.6 vcc/5.6 v pwm ramp offset guaranteed by characterization 0.64 v oscillator oscillator frequency range fsw fsw = 500 khz 4.5 v < vcc < 18 v 450 500 550 khz
ncp3231a www. onsemi.com 6 electrical characteristics (?40 c < t j < +125 c, v cc = 12 v, for min/max values unless otherwise noted, t j = +25 c for typical values) parameter units max typ min test conditions symbol oscillator hiccup timer t hiccup tss < 1 ms, fsw = 500 khz 4 ms tss > 1 ms, fsw = 500 khz 4 x tss ms enable input (en) en input operating range 5.5 v enable threshold voltage v_en ven rising 1.11 1.2 1.29 v enable hysteresis ven falling 144 mv deep disable threshold 0.7 0.78 0.9 v enable pull?up current 2 a softstart input (ss) ss startup delay tssd 1.33 ms ss end threshold ssend 0.6 v ss source current iss 2.15 2.5 2.8 a voltage monitor power good sink current pg = 0.15 v 10 20 30 ma output overvoltage rising thresh- old 665 675 685 mv overvoltage fault blanking time 20 s output under?voltage trip thresh- old 500 525 550 mv under?voltage protection blanking time 20 s ovp and uvp enable delay t ss s power stage high?side on resistance rdsonh vin/vcc = 5 v, id = 2 a 7 9.9 m low?side on resistance rdsonl vin/vcc = vb, id = 2 a 1.5 2.9 m vfboot iboot = 2 ma 0.28 v thermal monitor (ots) ots comparator reference voltage (rising threshold) 0.59 0.6 0.61 v ots comparator reference voltage (falling hysteresis) 50 mv thermal shutdown thermal shutdown threshold guaranteed by design 135 150 165 c thermal shutdown hysteresis guaranteed by design 25 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncp3231a www. onsemi.com 7 typical characteristics figure 3. reference voltage vs. temperature figure 4. switching frequency vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 95 80 65 35 5 ?10 ?25 ?40 0.596 0.597 0.598 0.599 0.600 0.601 0.602 498 499 500 501 502 503 504 figure 5. rising enable threshold vs. temperature figure 6. falling enable threshold vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 1.19 1.20 1.21 1.22 1.23 1.06 1.07 1.08 1.09 1.10 figure 7. shutdown current vs. temperature figure 8. quiescent current vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 110 80 50 20 5 ?10 ?25 ?40 0 10 30 40 50 70 80 100 0 1 2 3 4 5 6 7 v fb , feedback reference voltage (v) f sw , switching frequency (khz) v en , rising enable threshold (v) v en , falling enable threshold (v) i sd , shutdown current ( a) i q , quiescent current (ma) 20 50 110 125 95 80 65 35 5 ?10 ?25 ?40 20 50 110 125 v cc = 12 v v cc = 4.5 v 95 80 65 35 5 ?10 ?25 ?40 20 50 110 125 95 80 65 35 5 ?10 ?25 ?40 20 50 110 125 35 65 95 125 20 60 90 v cc = 12 v 110 80 50 20 5 ?10 ?25 ?40 35 65 95 125 v cc = 12 v, no switching
ncp3231a www. onsemi.com 8 typical characteristics figure 9. soft?start current vs. temperature figure 10. iset current vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 2.30 2.35 2.45 2.50 2.60 2.65 2.70 125 95 65 50 35 5 ?10 ?40 20 25 30 35 40 45 50 figure 11. high?side r ds(on) vs. temperature figure 12. low?side r ds(on) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 95 80 35 20 5 ?10 ?25 ?40 5.0 5.5 6.0 7.0 7.5 8.0 9.0 9.5 110 80 65 20 5 ?10 ?25 ?40 0 0.5 1.0 1.5 2.0 2.5 figure 13. efficiency vs. iout (vin = 12 v) figure 14. efficiency vs. iout (vin = 5 v) i out , load current (a) i out , load current (a) 22.5 20.0 15.0 12.5 7.5 5.0 2.5 0 50 55 65 70 80 85 95 100 22.5 20.0 15.0 12.5 10.0 5.0 2.5 0 60 65 70 75 85 90 95 100 i ss , soft?start current ( a) i set , lsocp set current ( a) high?side fet r ds(on) (m ) low?side fet r ds(on) (m ) efficiency (%) efficiency (%) 110 80 50 20 5 ?10 ?25 35 65 95 125 ?40 2.40 2.55 110 80 20 ?25 6.5 8.5 50 65 110 125 v in /v cc = 4.5 v v in /v cc = 12 v v in /v cc = 4.5 v v in /v cc = 12 v 35 50 95 125 60 75 90 10.0 17.5 25.0 v in /v cc = 12 v t a = 25 c v out = 1.0 v v out = 1.2 v v out = 1.8 v v out = 2.5 v v out = 3.3 v v in /v cc = 5 v t a = 25 c v out = 1.0 v v out = 1.2 v v out = 1.8 v v out = 2.5 v v out = 3.3 v 7.5 17.5 25.0 80
ncp3231a www. onsemi.com 9 typical characteristics figure 15. ots threshold vs. temperature figure 16. vb uvlo rising threshold vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.54 0.55 0.56 0.57 0.58 0.59 0.60 0.61 4.10 4.14 4.18 4.22 4.26 4.30 figure 17. vb uvlo falling threshold vs. junction temperature figure 18. output ovp vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 3.60 3.64 3.68 3.72 3.76 3.80 670 671 673 674 675 677 678 680 figure 19. output uvp vs. junction temperature t j , junction temperature ( c) 540 544 546 548 550 554 556 560 ots, overtemperature threshold voltage (v) vb uvlo rising threshold voltage (v) vb uvlo, falling threshold voltage (v) ovp, overvoltage threshold (v) uvp, undervoltage threshold (v) 110 80 50 20 5 ?10 ?25 ?40 35 65 95 125 rising threshold falling threshold 110 80 50 20 5 ?10 ?25 ?40 35 65 95 125 110 80 50 20 5 ?10 ?25 ?40 35 65 95 125 110 80 50 20 5 ?10 ?25 ?40 35 65 95 125 672 676 679 110 80 50 20 5 ?10 ?25 ?40 35 65 95 125 542 552 558
ncp3231a www. onsemi.com 10 typical characteristics figure 20. typical startup waveforms (vin = 12 v, iout = 25 v, vout = 1 v) figure 21. typical short circuit waveforms (vin = 12 v) ch1 (blue): vsw ch2 (aqua): comp ch3 (purple): vout ch4 (green): ss ch1 (blue): en ch2 (aqua): comp ch3 (purple): vout ch4 (green): ss
ncp3231a www. onsemi.com 11 operation description overview the ncp3231a is a 500 khz, high ef ficiency, high current pwm synchronous buck converter. it operates with a single supply voltage from 4.5 to 18 v and can provide output current as high as 25 a. ncp3231a utilizes voltage mode with voltage feed?forward control to respond instantly to vin changes and provide for easier compensation over the supply range of the converter. the device also includes pre?bias startup capability to allow monotonic startup in the event of a pre?biased output condition. protection features include overcurrent protection (ocp), output over and under voltage protection (ovp, uvp), and power good. the enable function is highly programmable to allow for adjustable startup voltages at higher input voltages. there is also an adjustable soft?start, an over? temperature/over?voltage comparator, and internal thermal shutdown. reference voltage the ncp3231a incorporates an internal reference that allows output voltages as low as 0.6 v. the tolerance of the internal reference is guaranteed over the entire operating temperature range of the controller. the reference voltage is trimmed using a test configuration that accounts for error amplifier offset and bias currents. oscillator ramp the ramp waveform is a saw tooth formed at the pwm frequency with a peak?to?peak amplitude of vcc/6.6, offset from gnd by typically 0.64 v. the pwm duty cycle is limited to a maximum of 92%, allowing the bootstrap capacitor to charge during each cycle. error amplifier the error amplifier?s primary function is to regulate the converter?s output voltage using a resistor divider connected from the converter?s output to the fb pin of the controller, as shown in the applications schematic. a type iii compensation network must be connected around the error amplifier to stabilize the converter . it has a bandwidth of greater than 24 mhz, with open loop gain of at least 60 db. programmable soft?start an external capacitor connected from the ss pin to ground sets up the soft start period, which can limit the start?up inrush current. the soft start period can be programmed based on the equation 1. t ss c ss v ref i ss (eq. 1) ocp is the only fault that is active during a soft?start. adaptive non?overlap gate driver in a synchronous buck converter, a certain dead time is required between the low side drive signal and high side drive signal to avoid shoot through. during the dead time, the body diode of the low side fet freewheels the current. the body diode has much higher voltage drop than that of the mosfet, which reduces the efficiency significantly. the longer the body diode conducts, the lower the efficiency. ncp3231a implements adaptive dead time control to minimize the dead time, as well as preventing shoot through. precision enable (en) the enable block allows the output to be toggled on and off and is a precision analog input. when the en voltage exceeds v_en, the controller will initiate the soft-start sequence as long as the input voltage and sub-regulated voltage have exceeded their uvlo thresholds. v_en_hyst helps to reject noise and allow the pin to be resistively coupled to the input voltage or sequenced with other rails. if the en voltage is held below typically 0.8 v, the ncp3231a enters a deep disable state where the internal bias circuitry is off. as the voltage at en continues to rise, the enable comparator and reference are active and provide a more accurate en threshold. the drivers are held off until the rising voltage at en crosses v_en. an internal 2 a pullup automatically enables the device when the en pin is left floating. figure 22. enable functional block diagram en vdd 1.2 v enable logic input supply / vcc 2 a pre?bias startup in some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 v to just below the regulation voltage. this situation occurs for a number of reasons: the converter?s output capacitors may have residual charge on them or the converter?s output may be held up by a low current standby power supply. ncp3231a supports pre?bias start up by holding of f switching until the feedback voltage and thus the output voltage rises above the set regulated voltage. if the pre?bias voltage is higher than the set regulated voltage, switching does not occur until the output voltage drops back to the regulation point.
ncp3231a www. onsemi.com 12 1 2 3 hiccup counter hiccup backup counter reset/start start start reset/start power good pullup voltage power good (pg) operation inductor current lsocp trip level skipped pulses showing skip count thiccup = 4xtss figure 23. lsocp function with counters and power good shown (exaggerated for informational purposes) protection features hiccup mode the ncp3231a utilizes hiccup mode for all of its fault conditions. upon entering hiccup mode after a fault detection, the ncp3231a turns off the high side and low side fet?s and pg goes low. it waits for thiccup ms before reinitiating a soft?start. thiccup is defined as four soft start timeouts (tss). and if the soft?start time tss is set to be less than 1 ms, the hiccup time will be 4 ms. the equation for tss is shown in equation 1. ocp is the only active fault detection during the hiccup mode soft start. over temperature comparator (ots) the ncp3231a provides an over?temperature shutdown (ots) comparator with 50 mv hysteresis and a 0.6 v reference in order to remotely sense an external temperature detector or thermistor. when the voltage at the ots pin rises above 0.6 v, the drivers stop switching and both fet?s remain of f. when this voltage drops below typically 0.55 v, a new soft?start cycle is generated automatically. tie the ots pin to ground if this function is not required. over voltage protection (ovp) when the voltage at the fb pin (vfb) is above the ovp threshold for greater than 20 s (typical), an ovp fault is set. the high side fet (hsfet) will turn off and the low side fet (lsfet) will turn on. the open-drain pg pull down will turn on at that point as well, thus pulling pg low. once vfb has fallen below the undervoltage protection threshold (uvp), the device will enter hiccup mode. under voltage protection (uvp) a uvp circuit monitors the vfb voltage to detect an under voltage event. if the vfb voltage is below this threshold for more than 20 s, a uvp fault is set and the device will enter hiccup mode. over current protection (ocp) the ncp3231a over current protection scheme senses the peak freewheeling current in the low?side fet (lsocp) after a blanking time of 150 ns as shown in figure 23. the low?side fet drain?to?source voltage, vds, is compared against the voltage of a fixed, internal current source, iset and a user?selected resistor, rset. voltage across the low?side fet is sensed from the vsw pin to gnd. after an ocp detection, the ncp3231a keeps the high?side fet off until the low?side fet current falls below the trip point again and the next clock cycle occurs. an internal ocp counter will count up to 3 consecutive lsocp events. after the third consecutive count, the device enters hiccup mode.
ncp3231a www. onsemi.com 13 to prevent nuisance trips, there is a backup counter that will reset the ocp counter after 7 consecutive cycles without an lsocp trigger. the backup counter is reset and then started again after each ocp trip until the third ocp count as stated above occurs. over current protection threshold the ncp3231a allows the user to adjust the lsocp threshold with an external resistor, rset. this resistor, along with an internal temperature compensated current source, iset, sets the current limit reference voltage for the lsocp comparator. internally, a current sense circuit samples the voltage from vsw to gnd. this voltage is then multiplied by a factor of 2 and compared against the iset*rset voltage threshold. the basic design equation for lsocp trip point selection is: 2 67 i load 0.5i lpk pk (eq. 2) rset 2 i load 0.5i lpk pk rdson iset in this equation, i load is the over current protection point of the load current, i lpk-pk is the peak to peak value of inductor current, and for example, when input voltage is 12 v, output voltage is 3.3 v, switching frequency is 500 khz and inductor value is 330 nh, the peak to peak value of inductor current is 14.5 a. iset is temperature compensated current source proportional to the on-resistance of ls mosfet, rdson, the ratio of rdson to iset is about 67. in case rset is not connected, the device switches the ocp threshold to a fixed 300 mv value: an internal safety clamp on iset is triggered as soon as the iset voltage reaches 600 mv, enabling the 300 mv fixed threshold. thermal shutdown (tsd) the ncp3231a protects itself from overheating with an internal thermal monitoring circuit. if the junction temperature exceeds the thermal shutdown threshold both the upper and lower mosfets will be shut off. once the temperature drops below the falling hysteresis threshold, the voltage at the comp pin will be pulled below the ramp valley voltage and a soft?start will be initiated. power good monitor (pg) ncp3231a monitors the output voltage and signal when the output is out of regulation or during a non?regulated pre?bias condition, or fault condition. when the output voltage is within the ovp and uvp thresholds, the power good pin is a high impedance output. if the ncp3231a detects an ocp, ovp, uvp, ots, tsd or is in soft start, it pulls pg pin low. the pg pin is an open drain 10 ma pull down output. layout guidelines when laying out a power pcb for the ncp3231a there are several general key points and special key points to consider: general layout guide: these are the common techniques for high frequency high power board layout design. base component placement: high current path components should be placed to keep the current path as tight as possible. placement of components on the bottom of the board such as input or output decoupling can add loop inductance. ground return for power and signals: solid, uninterrupted ground planes must be present and adjacent to the high current path. copper shapes on component layers: large copper planes on one or multiple layers with adequate vias will increase thermal transfer, reduce copper conduction losses, and minimize loop inductance. greater than 20 a designs require 2~3 layer shapes or more, increasing the number of layers will only improvement performance. via placement for power and ground: place enough vias to adequately connect outer layers to inner layers for thermal transfer and to minimize added inductance in layer transition. multiple vias should be placed near important components like input ceramics and output ceramic capacitors. key signal routes: do not route sensitive signals, such as fb near or under noisy nets such as the switch node vsw and bst node, to reduce noise coupling effects on the sensitive lines. special layout guide: please pay attention to the special requirement of layout guide. to improve the high-side ocp accuracy, users should connect vcc and vin directly and do not place any type of filter or resistor between these two pins. to improve the low-side ocp accuracy, users should use single ground connection instead of separate analog ground and power ground. make sure that the inner layers (at least 2nd layer, 3rd layer and 4th layer) are dedicated for ground plane. do not use other copper planes to cut or interrupt the shape of ground plane, which may add more parasitic components to affect the sensing accuracy.
ncp3231a www. onsemi.com 14 package dimensions qfn40 6x6, 0.5p case 485cm issue o seating 0.15 c (a3) a a1 b 1 40 2x 2x 40x l 40x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. 5. positional tolerance applies to all three exposed pads. dim min max millimeters a 0.80 1.00 a1 ??? 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 2.30 2.50 e 6.00 bsc 4.50 e2 4.30 e 0.50 bsc l 0.30 0.50 k 0.20 ??? plane soldering footprint d3 1.40 1.60 2.10 e3 1.90 l1 ??? 0.15 note 4 e/2 e2 d2 note 3 e3 43x detail b l1 detail a l alternate constructions l 2.20 bsc d3 e4 g detail a a 0.10 b c note 5 k dimensions: millimeters 2.16 6.30 4.56 4.56 2.56 0.50 0.63 0.30 40x 40x pitch 2.16 6.30 1.66 pkg outline 1 g g 1.84 e4 1.64 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp3231a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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